As the performance of digital devices is improving, Hardware-In-the-Loop (HIL) techniques\nare being increasingly used. HIL systems are frequently implemented using FPGAs (Field Programmable\nGate Array) as they allow faster calculations and therefore smaller simulation steps. As the simulation\nstep is reduced, the incremental values for the state variables are reduced proportionally, increasing the\ndifference between the current value of the state variable and its increments. This difference can lead to\nnumerical resolution issues when both magnitudes cannot be stored simultaneously in the state variable.\nFPGA-based HIL systems generally use 32-bit floating-point due to hardware and timing restrictions but\nthey may suffer from these resolution problems. This paper explores the limits of 32-bit floating-point\narithmetics in the context of hardware-in-the-loop systems, and how a larger format can be used to avoid\nresolution problems. The consequences in terms of hardware resources and running frequency are also\nexplored. Although the conclusions reached in this work can be applied to any digital device, they can be\ndirectly used in the field of FPGAs, where the designer can easily use custom floating-point arithmetics
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